TAS3218PZP datasheet(18/79 Pages) TI

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TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Table 2. Relationship of M8051 SFR Register Map With I2C Registers

RST:

Module reset

Normal operation

Reset SPDIF-TX module (default)

CP:

Copy permit

Copy prohibit (default)

Copy permit

EMP:

Pre-emphasis

No pre-emphasis (default)

50/15 s 2-channel pre-emphasis

CATEGORY:

Category code 7-bit device category code. Default: 0101010

(digital sound processor)

Generation status

Generation 1 or higher (default)

Original

SR:

Sampling rate

00:

44.1 kHz

01:

48 kHz (default)

10:

Reserved

11:

32 kHz

VL:

Validity for left channel

Left channel data is valid (default)

Left channel data is invalid

VR:

Validity for right channel

Right channel data is valid (default)

Right channel data is invalid

SRCNUM:

Source channel number

0000:

Not specified

0001:

0010:

2 (default)

0011:

. . .

1000:

CLKAC:

Clock accuracy

00:

Level II, 1000 ppm

01:

Level III, variable pitch shifted

10:

Level I, 50 ppm (default)

11:

Reserved

WORDLEN:

Sample bit size

0000:

24 bits (default)

0001:

23 bits

0010:

22 bits

. . .

20 bits

0100:

. . .

1000:

16 bits

Others:

Reserved

I2C Register Map for SPDIF

Figure 15 shows system accessible I2C register mapping for controlling the SPDIF module. The mute control

(MTE) uses the same control bits for controlling SDOUT2 mute at subaddress 0x09 and the module reset (RST)

is mapped to subaddress 0x10 together with other power down control bits. Other control bits are mapped to

subaddress 0x16.

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