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7470/7471/7477/7478 GROUP USER’S MANUAL

HARDWARE

1.11 Interrupts

1-57

1.11.4 Notes on use

(1) When using P30 to P33 as input ports, put the corresponding INT interrupt or the CNTR interrupt into

a disable state.

(2) Set the interrupt request bit and the interrupt enable bit for preparations for an interrupt in the

following order.

1 Clear the interrupt request bit to “0.” (No interrupt request)

2 Set the interrupt enable bit to “1.” (Interrupt enabled)

When using the INT interrupt or the CNTR interrupt, first set the interrupt detection edge and then

set the above items 1 and 2. (Refer to (4) that will be described later.)

(3) An interrupt request bit can be cleared to “0” by software, but is still remained at the value precedent

to a change immediately after execution of the clear instruction. For this reason, when executing

the BBC or BBS instruction after changing an interrupt request bit, first execute the interrupt request

bit change instruction and then execute the BBC or BBS instruction after one instruction or more.

(4) When the detection edge of the INT interrupt or that of the CNTR interrupt is switched, the corresponding

interrupt request bit may be set to “1.” Accordingly, perform setting referring to the register setting

example shown in Figure 1.11.7.

Fig. 1.11.7 Example of register setting

(5) Whether an interrupt is caused by the BRK instruction or not can be judged by the contents of the

break flag of the Processor status register pushed on the stack area.

q Break flag = “1” : An interrupt has been caused by the BRK instruction

q Break flag = “0” : In case of the other interrupts

Note: Make this judgment in the interrupt processing routine.

(6) When an INT interrupt request is generated by executing the STP/WIT instruction in one of the

following states, the stop mode/wait mode is released.

q When the active edge of the INT interrupt is a rising edge and the INT pin input level is “H”

q When the active edge of the INT interrupt is a falling edge and the INT pin input level is “L”

Accordingly, when executing the STP/WIT instruction, it is necessary to consider the input level of

the INT pin and the polarity of the INT edge. Examples of countermeasures for it are shown below.

1. An example of a countermeasure for the case where the stop mode/wait mode is released at the

rising edge of the INT pin input level

Point: To release the stop mode/wait mode normally, perform mode release processing in the

INT interrupt processing routine only when the STP/WIT instruction was executed at the

“L” INT pin input level.

Clear the corresponding interrupt enable bit to “0”

Set the corresponding interrupt enable bit to “1”

Clear the corresponding interrupt request bit to “0”

Set the interrupt active edge

Execute one or more instructions (NOP instruction, and so on)

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