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7733 датащи(PDF) 243 Page - Renesas Technology Corp |
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7733 датащи(HTML) 243 Page - Renesas Technology Corp |
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243 / 940 page ![]() SERIAL I/O 7733 Group User’s Manual 8–40 8.3 Clock synchronous serial I/O mode TxDi RxDi CLKi CTSi TxDi RxDi CLKi RTSi (Note) Transmitter side Receiver side Note: The RTSi output function is not assigned for Clock which is output from or input to CLKi pin UARTi receive buffer register UARTi receive register D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D0 Receive data MSB b7 b0 LSB D2 D1 D0 g This is applied when the CLK polarity selection bit = “0.” When the CLK polarity selection bit = “1,” data is shifted at the falling edge of the clock which is output from or input to the CLKi pin. Fig. 8.3.14 Receive operation Fig. 8.3.13 Connection example |
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