7733 datasheet(180/940 Pages) RENESAS

180 / 940 page

TIMER B

7733 Group User’s Manual

7–17

7.4 Event counter mode (Bits 1 and 0 of timer Bi mode register = “012”)

In this mode, an external signal is counted. (Refer to Table 7.4.1.) Figure 7.4.1 shows the structures of the

timer Bi mode register and timer Bi register in the event counter mode.

Table 7.4.1 Specifications of event counter mode

Specifications

q External signal input to pin TBiIN (Notes 1 and 2).

q “Falling edge,” “Rising edge,” or “Falling and Rising edges” can be

selected as the valid edge of the count source by software.

q Countdown

q At an underflow, the reload register’s contents is reloaded, and

counting is continued.

n: Set value in the timer Bi register

When the count start flag is set to “1.”

When the count start flag is cleared to “0.”

At an underflow

Count source input

A counter value can be read out by reading the timer Bi register.

s While counting is stopped

When a value is written to the timer Bi register, it is written to both

of the reload register and counter.

s While counting is in progress

When a value is written to the timer Bi register, it is written only to

the reload register. (Transferred to the counter at the next reload

time.)

Item

Count source

Count operation

Division ratio

Count start condition

Count stop condition

Interrupt request occurrence timing

Pin TBiIN’s function

Read from timer

Write to timer

(n + 1)

Notes 1: When the timer B1 internal connect selection bit (bit 2 at address 6D16) = “1,” timer B1 counts

the timer B2’s underflow signal. (Refer to section “7.4.3 Selectable functions.”)

2: When using timer B2 in the event counter mode, set both of the port-Xc selection bit (bit 4 at

address 6C16) and the sub-clock output selection bit/Timer B2 clock source selection bit (bit 1 at

address 6D16) to “0.” When one of or both of these bits = “1,” timer B2 functions as a clock timer.

(Refer to section “7.6 Clock timer.”)

7.4 Event counter mode

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