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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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7733 датащи(PDF) 174 Page - Renesas Technology Corp |
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7733 датащи(HTML) 174 Page - Renesas Technology Corp |
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174 / 940 page  TIMER B 7733 Group User’s Manual 7–11 Fig. 7.3.1 Structures of timer Bi mode register and timer Bi register in timer mode At reset 0 0 Un- defined Un- defined 0 0 RW Bit 3 Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register (i = 0 to 2) (addresses 5B16 to 5D16) b1 b0 b4 b3 0 0 X X X 0 0 0 7 0 0: Clock f2 0 1: Clock f16 1 0: Clock f64 1 1: Clock f512 b7 b6 6 Count source selection bits 5 This bit is ignored in the timer mode and is undefined at reading. Clocks f2, f16, f64, and f512: Refer to chapter “14. CLOCK GENERATING CIRCUIT.” b7 b0 b7 b0 (b15) (b8) Timer B0 register (addresses 5116, 5016) Timer B1 register (addresses 5316, 5216) Timer B2 register (addresses 5516, 5416) Functions Bit At reset RW 15 to 0 Values 000016 to FFFF16 can be set. Assuming that the set value = n, counter divides the count source frequency by (n + 1). At reading this register, the counter value is read out. Un- defined 2 These bits are ignored in the timer mode. 1 0 Operating mode selection bits 0 0: Timer mode 4 •Timer B0 mode register Must be fixed to “0.” •Timer B1 and B2 mode registers Not implemented. RW RW RW RW RW — RO RW RW RW 7.3 Timer mode |
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