3886 datasheet(21/380 Pages) RENESAS

21 / 380 page

3886 Group User’s Manual

List of figures

Fig. 2.10.1 Memory map of registers relevant to watchdog timer ...................................... 2-137

Fig. 2.10.2 Structure of Watchdog timer control register ..................................................... 2-137

Fig. 2.10.3 Structure of CPU mode register .......................................................................... 2-138

Fig. 2.10.4 Watchdog timer connection and division ratio setting ...................................... 2-139

Fig. 2.10.5 Relevant registers setting ..................................................................................... 2-140

Fig. 2.10.6 Control procedure ................................................................................................... 2-140

Fig. 2.11.1 Example of poweron reset circuit ........................................................................ 2-141

Fig. 2.11.2 RAM backup system .............................................................................................. 2-141

Fig. 2.12.1 Structure of CPU mode register .......................................................................... 2-143

Fig. 2.12.2 Connection diagram ............................................................................................... 2-144

Fig. 2.12.3 Status transition diagram during power failure .................................................. 2-144

Fig. 2.12.4 Setting of relevant registers ................................................................................. 2-145

Fig. 2.12.5 Control procedure ................................................................................................... 2-146

Fig. 2.13.1 Oscillation stabilizing time at restoration by reset input .................................. 2-148

Fig. 2.13.2 Execution sequence example at restoration by occurrence of INT0 interrupt request .. 2-150

Fig. 2.13.3 Reset input time ..................................................................................................... 2-152

Fig. 2.14.1 Memory map of registers relevant to processor mode ..................................... 2-154

Fig. 2.14.2 Structure of CPU mode register .......................................................................... 2-154

Fig. 2.14.3 Expansion example of 32-Kbytes ROM and RAM ............................................ 2-155

Fig. 2.14.4 Read cycle (OE access, SRAM) .......................................................................... 2-156

Fig. 2.14.5 Read cycle (OE access, EPROM) ....................................................................... 2-156

Fig. 2.14.6 Write cycle (W control, SRAM) ............................................................................ 2-157

Fig. 2.14.7 Usage example of ONW function ........................................................................ 2-158

Fig. 2.14.8 Expansion example of 32-Kbytes ROM and RAM at f(XIN) = 8 MHz or more ... 2-159

Fig. 2.14.9 Read cycle (OE access, SRAM) .......................................................................... 2-160

Fig. 2.14.10 Read cycle (OE access, EPROM) ..................................................................... 2-160

Fig. 2.14.11 Write cycle (W control, SRAM) .......................................................................... 2-161

Fig. 2.15.1 Memory map of flash memory version for 3886 Group ................................... 2-162

Fig. 2.15.2 Memory map of registers relevant to flash memory ......................................... 2-163

Fig. 2.15.3 Structure of Flash memory control register ........................................................ 2-163

Fig. 2.15.4 Structure of Flash command register .................................................................. 2-164

Fig. 2.15.5 Reprogramming example of built-in flash memory in serial I/O mode ........... 2-167

Fig. 2.15.6 Connection example in serial I/O mode (1) ....................................................... 2-168

Fig. 2.15.7 Connection example in serial I/O mode (2) ....................................................... 2-168

Fig. 2.15.8 Connection example in serial I/O mode (3) ....................................................... 2-169

Fig. 2.15.9 Example of reprogramming system for built-in flash memory in CPU reprogramming mode ... 2-170

Fig. 2.15.10 CPU reprogramming control program example (1) ......................................... 2-171

Fig. 2.15.11 CPU reprogramming control program example (2) ......................................... 2-172

Fig. 2.15.12 CPU reprogramming control program example (3) ......................................... 2-173

Fig. 2.15.13 CPU reprogramming control program example (4) ......................................... 2-174

Fig. 2.15.14 VPP control circuit example (1) ........................................................................... 2-175

Fig. 2.15.15 VPP control circuit example (2) ........................................................................... 2-175

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ................................... 3-12

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ................................... 3-12

Fig. 3.1.3 Timing diagram (1) (in single-chip mode) ............................................................... 3-13

Fig. 3.1.4 Timing diagram (2) (in memory expansion mode and microprocessor mode) .. 3-14

Fig. 3.1.5 Timing diagram (3) (in memory expansion mode and microprocessor mode) .. 3-15

Fig. 3.1.6 Timing diagram (4) (system bus interface) ............................................................ 3-16

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