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4502 датащи(PDF) 46 Page - Renesas Technology Corp |
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4502 датащи(HTML) 46 Page - Renesas Technology Corp |
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46 / 214 page ![]() FUNCTION BLOCK OPERATIONS 1-34 Rev.2.01 Feb 02, 2005 4502 Group HARDWARE REJ09B0193-0201 Table 13 Change of successive comparison register AD during A/D conversion Comparison voltage (Vref) value Change of successive comparison register AD At starting conversion ± ± ± ± ± ✼1: 1st comparison result ✼3: 3rd comparison result ✼9: 9th comparison result ✼2: 2nd comparison result ✼8: 8th comparison result ✼A: 10th comparison result 1st comparison 2nd comparison 3rd comparison After 10th comparison completes 1 ✼1 ✼1 ✼1 ----- ----- ----- ----- 0 1 ✼2 ✼2 0 0 1 ✼3 0 0 0 ✼8 0 0 0 ✼9 0 0 0 ✼A A/D conversion result VDD 2 VDD 2 VDD 2 VDD 2 VDD 4 VDD 4 VDD 8 VDD 1024 ------------- ------------- ------------- ------------- ------------- ------------- ------------- ------------- Fig. 30 Setting registers A/D control register Q1 AIN1 pin selected A/D conversion mode 0 001 (Bit 3) (Bit 0) (7) A/D conversion timing chart Figure 29 shows the A/D conversion timing chart. Fig. 29 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P21/AIN1 pin is A/D converted, and the high- order 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. ➀ Select the AIN1 pin function and A/D conversion mode with the register Q1 (refer to Figure 30). ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to de- termine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). ADST instruction A/D conversion completion flag (ADF) 62 machine cycles DAC operation signal |
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