SH7641 datasheet(21/1040 Pages) RENESAS

21 / 1040 page

Rev. 2.00 Mar. 15, 2007 Page xxi of l

18.3.2 Timer Mode Register (TMDR) ............................................................................. 530

18.3.3 Timer I/O Control Register (TIOR) ...................................................................... 532

18.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 550

18.3.5 Timer Status Register (TSR)................................................................................. 552

18.3.6 Timer Counter (TCNT)......................................................................................... 555

18.3.7 Timer General Register (TGR) ............................................................................. 555

18.3.8 Timer Start Register (TSTR) ................................................................................ 556

18.3.9 Timer Synchro Register (TSYR) .......................................................................... 556

18.3.10 Timer Output Master Enable Register (TOER) .................................................... 558

18.3.11 Timer Output Control Register (TOCR) ............................................................... 559

18.3.12 Timer Gate Control Register (TGCR) .................................................................. 561

18.3.13 Timer Subcounter (TCNTS) ................................................................................. 563

18.3.14 Timer Dead Time Data Register (TDDR)............................................................. 563

18.3.15 Timer Period Data Register (TCDR) .................................................................... 563

18.3.16 Timer Period Buffer Register (TCBR).................................................................. 563

18.3.17 Bus Master Interface ............................................................................................. 564

18.4

Operation ........................................................................................................................... 564

18.4.1 Basic Functions..................................................................................................... 564

18.4.2 Synchronous Operation......................................................................................... 570

18.4.3 Buffer Operation ................................................................................................... 573

18.4.4 Cascaded Operation .............................................................................................. 576

18.4.5 PWM Modes ......................................................................................................... 578

18.4.6 Phase Counting Mode ........................................................................................... 583

18.4.7 Reset-Synchronized PWM Mode.......................................................................... 590

18.4.8 Complementary PWM Mode................................................................................ 593

18.5

Interrupts............................................................................................................................ 618

18.5.1 Interrupts and Priority ........................................................................................... 618

18.5.2 DMA Activation ................................................................................................... 620

18.5.3 A/D Converter Activation..................................................................................... 620

18.6

Operation Timing............................................................................................................... 621

18.6.1 Input/Output Timing ............................................................................................. 621

18.6.2 Interrupt Signal Timing......................................................................................... 626

18.7

Usage Notes ....................................................................................................................... 629

18.7.1 Module Standby Mode Setting ............................................................................. 629

18.7.2 Input Clock Restrictions ....................................................................................... 629

18.7.3 Caution on Period Setting ..................................................................................... 630

18.7.4 Conflict between TCNT Write and Clear Operations .......................................... 630

18.7.5 Conflict between TCNT Write and Increment Operations ................................... 631

18.7.6 Conflict between TGR Write and Compare Match............................................... 632

18.7.7 Conflict between Buffer Register Write and Compare Match .............................. 632

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