SH7641 datasheet(86/1040 Pages) RENESAS

номер детали	SH7641

подробное описание детали	Renesas 32-Bit RISC Microcomputer SuperH??RISC engine Family / SH7641 Series

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Section 2 CPU

Rev. 2.00 Mar. 15, 2007 Page 36 of 986

REJ09B0346-0200

When data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the

this operation, but no other registers can be stored.

The third kind of operation is a single-data transfer instruction, "MOVS.W" or "MOVS.L". These

instructions access any memory location through the LDB (figure 2.8). All DSP registers connect

to the LDB and can be the source or destination register of the data transfer. These instructions

have word and longword access modes. In word mode, registers to be loaded or stored by this

instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G.

When data is loaded into a register other than A0G and A1G in word mode, the lower half of the

half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an

8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0

or A1, it is sign-extended to bits 39 to 32.

Tables 2.2 and 2.3 show the data type of registers used in DSP instructions. Some instructions

cannot use some registers shown in the tables because of instruction code limitations. For

example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details

of register selectability.

SH7641 датащи(PDF) 86 Page - Renesas Technology Corp