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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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R8C/15 датащи(PDF) 164 Page - Renesas Technology Corp |
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R8C/15 датащи(HTML) 164 Page - Renesas Technology Corp |
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164 / 277 page  R8C/14 Group, R8C/15 Group 15. Clock Synchronous Serial I/O with Chip Select (SSU) Rev.2.10 Jan 19, 2006 Page 152 of 253 REJ09B0164-0210 15.3 Interrupt Requests SSU has five interrupt requests : transmit data empty, transmit end, receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the SSU interrupt vector table, determining interrupt sources by flags is required. Table 15.2 shows the SSU Interrupt Requests. CEIE, RIE, TEIE and TIE : Bits in SSER register ORER, RDRF, TEND and TDRE : Bits in SSSR register Generation conditions of Table 15.2 are met, a SSU interrupt request is generated.Set the each interrupt source to “0” by a SSU interrupt routine. However, the TDRE and TEND bits are automatically set to “0” by writing the transmit data to the SSTDR register and the RDRF bit is automatically set to “0” by reading the SSRDR register. When writing the transmit data to the SSTDR register, at the same time the TDRE bit is set to “1” (data is transmitted from the SSTDR to SSTRSR registers) again and when setting the TDRE bit to “0” (data is not transmitted from the SSTDR to SSTRSR registers), additional 1-byte data may be transmitted. Table 15.2 SSU Interrupt Requests Interrupt Request Abbreviation Generation Condition Transmit Data Empty TXI TIE=1, TDRE=1 Transmit End TEI TEIE=1, TEND=1 Receive Data Full RXI RIE=1, RDRF=1 Overrun Error OEI RIE=1, ORER=1 Conflict Error CEI CEIE=1, CE=1 |
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