R8CSLASH15 datasheet(90/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

12. Watchdog Timer

Rev.2.10

Jan 19, 2006

Page 78 of 253

REJ09B0164-0210

12. Watchdog Timer

The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is

recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can

select count source protection mode is enabled or disabled. Table 12.1 lists the Count Source Protection

Mode is Enabled / Disabled

Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.

Figure 12.1 shows the Block Diagram of Watchdog Timer and Figures 12.2 to 12.3 show the OFS, WDC,

WDTR, WDTS and CSPR Registers.

Figure 12.1

Block Diagram of Watchdog Timer

Table 12.1

Count Source Protection Mode is Enabled / Disabled

Item

When Count Source Protection

Mode is Disabled

When Count Source Protection

Mode is Enabled

Count Source

CPU clock

Low-speed on-chip oscillator

clock

Count Operation

Decrement

Reset Condition of Watchdog

Timer

• Reset

• Write “00h” to the WDTR register before writing “FFh”

• Underflow

Count Start Condition

Either of following can be selected

• After reset, count starts automatically

• Count starts by writing to WDTS register

Count Stop Condition

Stop mode, wait mode

None

Operation at the time of

Underflow

Watchdog timer interrupt or

watchdog timer reset

Watchdog timer reset

CPU Clock

1/16

1/128

Watchdog Timer

Internal

Reset Signal

Write to WDTR register

WDC7=0

WDC7=1

Set to

“7FFFh”(1)

PM12=1

Watchdog

Timer Reset

PM12=0

Watchdog Timer

Interrupt Request

Prescaler

CSPRO=0

fRING-S

CSPRO=1

CSPRO : Bit in CSPR register

WDC7 : Bit in WDC register

NOTES:

1. When the CSPRO bit is set to “1” (count source protection mode enabled), “0FFFh” is set.

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