R8CSLASH15 datasheet(152/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 140 of 253

REJ09B0164-0210

15. Clock Synchronous Serial I/O with Chip Select (SSU)

The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip

select (hereinafter referred to as SSU). Table 15.1 shows a SSU Specification and Figure 15.1 shows a

Block Diagram of SSU.

Figure 15.2 to 15.8 show SSU Associated Registers.

NOTES:

1. The interrupt vector table is one of the SSU.

2. When setting to the slave device, do not transmit continuously.

Table 15.1

SSU Specification

Item

Specification

Transfer Data Format

• Transfer-data length 8 bits

Continuous transmit and receive of serial data are enabled since both

transmitter and receiver have buffer structure.(2)

Operating Mode

• Clock synchronous communication mode

• 4-wire bus communication mode (including bidirectional communication)

Master / Slave Device

Selectable

I/O Pin

SSCK (I/O) : Clock I/O pin

SSI (I/O) : Data I/O pin

SSO (I/O) : Data I/O pin

SCS (I/O) : Chip-select I/O pin

Transfer Clock

• When the MSS bit in the SSCRH register is set to “0” (operates as slave

device), external clock can be selected.

• When the MSS bit in the SSCRH register is set to “1” (operates as master

device), internal clock (selects from

φ/256, φ/128, φ/64, φ/32, φ/16, φ/8 and φ/4

and outputs from SSCK pin) can be selected.

• Clock polarity and phase of SSCK can be selected.

Receive Error Detection • Overrun error

Overrun error occurs during receive and completes by error. While the RDRF

bit in the SSSR register is set to “1” (data in the SSRDR register) and

completing the next serial data receive, the ORER bit is set to “1”.

Multimaster Error

Detection

• Conflict error

While the SSUMS bit in the SSMR2 register is set to “1” (4-wire bus

communication mode) and the MSS bit in the SSCRH register is set to “1”

(operates as master device) and when starting a serial communication, the

CE bit in the SSSR register is set to “1” if “L” applies to the SCS pin input.

When the SSUMS bit in the SSMR2 register is set to “1” (4-wire bus

communication mode), the MSS bit in the SSCRH register is set to “0”

(operates as slave device) and the SCS pin input changes state from “L” to

“H”, the CE bit in the SSSR register is set to “1”.

Interrupt Request

5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,

overrun error and conflict error).(1)

Select Function

• Data transfer direction

Selects MSB-first or LSB-first

• SSCK clock polarity

Selects “L” or “H” level when clock stops

• SSCK clock phase

Selects edge of data change and data download

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