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SH7750 датащи(PDF) 28 Page - Renesas Technology Corp |
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SH7750 датащи(HTML) 28 Page - Renesas Technology Corp |
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28 / 1162 page ![]() Rev.7.00 Oct. 10, 2008 Page xxviii of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) 19.1.2 Block Diagram Figure 19.1 Block Diagram of INTC 826 Figure amended Interrupt request IMASK SR CPU 19.1.3 Pin Configuration Table 19.1 INTC Pins 827 Table amended Pin Name Abbreviation I/O Function Nonmaskable interrupt input pin NMI Input Input of nonmaskable interrupt request signal Interrupt input pins IRL3–IRL0 Input Input of interrupt request signals (maskable by IMASK in SR) 19.2.1 NMI Interrupt 828 Description amended NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK) in the status register (SR). 19.2.2 IRL Interrupts 830 Description amended The interrupt mask bits (IMASK) in the status register (SR) are not affected by IRL interrupt handling. 19.2.3 On-Chip Peripheral Module Interrupts 831 Description amended The interrupt mask bits (IMASK) in the status register (SR) are not affected by on-chip peripheral module interrupt handling. |
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