SH7205 datasheet(28/1904 Pages) RENESAS

28 / 1904 page

Rev. 1.00 Mar. 25, 2008 Page xxviii of xxxii

26.3.12 Operation Mode Setting Register for Blitter (GR_BLTMODE) ........................ 1361

26.3.13 Resize Display Setting Register for Graphics (GR_RISZSET) .......................... 1363

26.3.14 Resize Mode Select Register for Blitter (GR_RISZMOD)................................. 1365

26.3.15 Resize Delta Setting Register for Blitter (GR_DELT) ....................................... 1366

26.3.16 Resize Horizontal Starting Phase Register for Blitter (GR_HSPHAS) .............. 1368

26.3.17 Resize Vertical Starting Phase Register for Blitter (GR_VSPHAS)................... 1369

26.3.18 Resize Horizontal Delta Setting Register for Output Block (MGR_HDELT).... 1370

26.3.19 Resize Horizontal Starting Phase Register for Output Block (MGR_HPHAS).. 1371

26.3.20 Logical Operation Input Data Register for Blitter (GR_LGDAT) ...................... 1372

26.3.21 Chromakey Target Color Data Register for Blitter (GR_DETCOL) .................. 1373

26.3.22 Replacement Color Data Register for Blitter Blending (GR_BRDCOL) ........... 1374

26.3.23 Blend 1 Control Register for Blitter (GR_BRD1CNT) ...................................... 1375

26.3.24 Mixing Mode Setting Register for Output Block (MGR_MIXMODE).............. 1378

26.3.25 Panel-Output Horizontal Timing Setting Register for Output-Block

(MGR_MIXHTMG) ........................................................................................... 1381

26.3.26 Panel-Output Mixing Horizontal Valid Area Setting Register for Output

Block (MGR_MIXHS) ....................................................................................... 1382

26.3.27 Panel-Output Vertical Timing Setting Register for Output-Block

(MGR_MIXVTMG) ........................................................................................... 1383

26.3.28 Panel-Output Mixing Vertical Valid Area Setting Register for Output Block

(MGR_MIXVS).................................................................................................. 1384

26.3.29 Graphics Block Output SYNC Position Setting Register (GR_VSDLY) ........... 1385

26.3.30 Video DAC Timing Setting Register (VDAC_TMC) ........................................ 1386

26.4

Operation ......................................................................................................................... 1387

26.4.1 Input and Output Operations............................................................................... 1389

26.4.2 How to Use the DMA ......................................................................................... 1401

26.4.3 Blitter Operation ................................................................................................. 1406

26.4.4 Output Operations............................................................................................... 1458

26.4.5 Interrupts............................................................................................................. 1463

26.5

Appendix. VIDEO OUT (D/A Converter)....................................................................... 1468

26.5.1 Analog Output Current ....................................................................................... 1468

26.5.2 Notes on Usage ................................................................................................... 1471

26.5.3 Application Example .......................................................................................... 1472

Section 27 Pin Function Controller (PFC) ...................................................... 1473

27.1

Features............................................................................................................................ 1481

27.2

Register Descriptions ....................................................................................................... 1482

27.2.1 Port A I/O Register L (PAIORL)........................................................................ 1484

27.2.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4)................................ 1484

27.2.3 Port B I/O Register H (PBIORH) ....................................................................... 1486

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