SH7205 datasheet(13/1904 Pages) RENESAS

13 / 1904 page

Rev. 1.00 Mar. 25, 2008 Page xiii of xxxii

Section 8 User Break Controller (UBC) ............................................................221

8.1

Features.............................................................................................................................. 222

8.2

Input/Output Pin................................................................................................................. 224

8.3

Register Descriptions ......................................................................................................... 224

8.3.1

Break Address Register (BAR)............................................................................. 225

8.3.2

Break Address Mask Register (BAMR) ............................................................... 226

8.3.3

Break Data Register (BDR) .................................................................................. 227

8.3.4

Break Data Mask Register (BDMR) ..................................................................... 228

8.3.5

Break Bus Cycle Register (BBR).......................................................................... 229

8.3.6

Break Control Register (BRCR) ........................................................................... 231

8.4

Operation ........................................................................................................................... 234

8.4.1

Flow of the User Break Operation ........................................................................ 234

8.4.2

Break on Instruction Fetch Cycle.......................................................................... 235

8.4.3

Break on Data Access Cycle................................................................................. 236

8.4.4

Value of Saved Program Counter ......................................................................... 237

8.4.5

Usage Examples.................................................................................................... 238

8.5

Usage Notes ....................................................................................................................... 241

Section 9 Cache .................................................................................................243

9.1

Features.............................................................................................................................. 243

9.1.1

Cache Structure..................................................................................................... 243

9.2

Register Descriptions ......................................................................................................... 246

9.2.1

Cache Control Register 1 (CCR1) ........................................................................ 246

9.2.2

Cache Control Register 2 (CCR2) ........................................................................ 248

9.3

Operation ........................................................................................................................... 252

9.3.1

Searching Cache ................................................................................................... 252

9.3.2

Read Access.......................................................................................................... 254

9.3.3

Prefetch Operation (Only for Operand Cache) ..................................................... 254

9.3.4

Write Operation (Only for Operand Cache).......................................................... 255

9.3.5

Write-Back Buffer (Only for Operand Cache)...................................................... 256

9.3.6

Coherency of Cache and External Memory .......................................................... 258

9.4

Memory-Allocated Cache .................................................................................................. 258

9.4.1

Address Array ....................................................................................................... 258

9.4.2

Data Array ............................................................................................................ 259

9.4.3

Usage Examples.................................................................................................... 261

9.4.4

Notes ..................................................................................................................... 261

Section 10 Bus State Controller (BSC)..............................................................263

10.1

Features.............................................................................................................................. 263

10.2

Input/Output Pins ...............................................................................................................265

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