HD6433044F datasheet(13/905 Pages) RENESAS

13 / 905 page

Rev. 7.00 Sep 21, 2005 page xiii of xxiv

Section 5

Interrupt Controller........................................................................................ 91

5.1

Overview........................................................................................................................... 91

5.1.1

Features................................................................................................................ 91

5.1.2

Block Diagram ..................................................................................................... 92

5.1.3

Pin Configuration................................................................................................. 93

5.1.4

5.2

Register Descriptions ........................................................................................................94

5.2.1

System Control Register (SYSCR) ...................................................................... 94

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 95

5.2.3

IRQ Status Register (ISR).................................................................................... 102

5.2.4

IRQ Enable Register (IER) .................................................................................. 103

5.2.5

IRQ Sense Control Register (ISCR) .................................................................... 104

5.3

Interrupt Sources ............................................................................................................... 105

5.3.1

External Interrupts................................................................................................ 105

5.3.2

Internal Interrupts................................................................................................. 106

5.3.3

Interrupt Vector Table.......................................................................................... 106

5.4

Interrupt Operation............................................................................................................ 110

5.4.1

Interrupt Handling Process................................................................................... 110

5.4.2

Interrupt Sequence ............................................................................................... 115

5.4.3

Interrupt Response Time...................................................................................... 116

5.5

Usage Notes ...................................................................................................................... 117

5.5.1

Contention between Interrupt and Interrupt-Disabling Instruction ...................... 117

5.5.2

Instructions that Inhibit Interrupts........................................................................ 118

5.5.3

Interrupts during EEPMOV Instruction Execution .............................................. 118

5.5.4

Usage Notes on External Interrupts ..................................................................... 118

5.5.5

Notes on Non-Maskable Interrupts (NMI)........................................................... 120

Section 6

Bus Controller ................................................................................................. 123

6.1

Overview........................................................................................................................... 123

6.1.1

Features................................................................................................................ 123

6.1.2

Block Diagram ..................................................................................................... 124

6.1.3

Input/Output Pins ................................................................................................. 125

6.1.4

6.2

Register Descriptions ........................................................................................................ 126

6.2.1

Bus Width Control Register (ABWCR)............................................................... 126

6.2.2

Access State Control Register (ASTCR) ............................................................. 127

6.2.3

Wait Control Register (WCR).............................................................................. 128

6.2.4

Wait State Controller Enable Register (WCER) .................................................. 129

6.2.5

Bus Release Control Register (BRCR) ................................................................ 130

6.2.6

Chip Select Control Register (CSCR).................................................................. 131

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