M32CSLASH86T datasheet(157/505 Pages) RENESAS

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Page 134

13. DMAC

)

(

13.2 DMAC Transfer Cycle

The number of DMAC transfer cycle can be calculated as follows.

Any combination of even or odd transfer read and write addresses are possible. Table 13.3 lists the number

of DMAC transfer cycles. Table 13.4 lists coefficient j, k.

Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k

Table 13.3 DMAC Transfer Cycles

Single-Chip Mode

Memory Expansion Mode

Microprocessor Mode

Transfer Unit

Bus Width

Access Address

Read

Write

Read

Write

Cycle

16-bit

Even

8-bit transfers

Odd

(BWi bit in the DMDp

8-bit

Even

——

Odd

——

16-bit

Even

16-bit transfers

Odd

(BWi bit = 1)

8-bit

Even

——

Odd

——

i= 0 to 3, p = 0, 1

Table 13.4 Coefficient j, k

Internal Space

External Space

Internal ROM

SFR

or internal RAM

area

j and k BCLK cycles shown in Table 8.5.

with no wait state with a wait state

Add one cycle to j or k cycles when inserting a recovery cycle.

j=1

j=2

k=1

k=2

j, k=2 to 9

13.3 Channel Priority and DMA Transfer Timing

When multiple DMA requests are generated in the same sampling period, between the falling edge of the

CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested)

simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3.

Figure 13.7 shows an example of the DMA transfer by external source.

In Figure 13.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0

request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus

privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts.

After one DMA1 transfer is completed, the privilege is again returned to the CPU.

In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when

DMA requests, as DMA1 in Figure 13.7, occur more than once before receiving bus privilege, the DRQ bit

is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is

completed.

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