M32CSLASH86T datasheet(140/505 Pages) RENESAS

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11. Interrupts

)

(

Bit 1

IIOiIR Register(2)

Intelligent I/O Interrupt i Request

IIOiIE Register(3)

IRLT Bit in

IIOiIE Register

Interrupt Request(1)

Bit 2

Bit 7

Bit 1

Bit 2

Bit 7

i= 0 to 5, 8 to 11

NOTES:

1. See Figures 11.14 and 11.15 about bits 1 to 7 in the

IIOiIR register and bits 1 to 7 in the IIOiIE register.

2. Bits 1 to 7 in the IIOiIR register are not set to "0"

automatically even if an interrupt request is

generated. Set to "0" by program.

3. Do not change the IRLT bit and the interrupt enable bit

in the IIOiIE register simultaneously.

11.11 Intelligent I/O Interrupt and CAN Interrupt

The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 49, 52 to 54,

and 57.

When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 5, 8

to 11) to "1" (interrupt request for interrupt used).

Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is gener-

ated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1"

(interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the

IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested).

After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set

to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1".

Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit

to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored.

Figure 11.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 11.14 shows

the IIOiIR register. Figure 11.15 shows the IIOiIE register.

Figure 11.13 Intelligent I/O Interrupt and CAN Interrupt

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