M32CSLASH86T datasheet(138/505 Pages) RENESAS

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Page 115

11. Interrupts

)

(

Interrupt Control

Circuit

KUPIC Register

Key Input Interrupt

Request

P107/KI3

P106/KI2

P105/KI1

P104/KI0

PU31 Bit in the

PUR3 Register

PD10_7 Bit

Pull-up

Transistor

PD10_7 Bit

PD10_6 Bit

PD10_5 Bit

PD10_4 Bit

Pull-up

Transistor

Pull-up

Transistor

Pull-up

Transistor

PSC_7 Bit

______

11.8 NMI Interrupt(1)

______

The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a

______

low-level ("L") signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as

______

the NMI interrupt input pin, the P8_5 bit in the P8 register indicates the input level for this pin.

NOTES:

______

1. When the NMI interrupt is not used, connect the NMI pin to VCC via a resistor. Because the NMI

interrupt cannot be ignored, the pin must be connected.

11.9 Key Input Interrupt

Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input

mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait

or stop mode. To use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 11.11

shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode,

signals applied to other pins are not detected as an interrupt request signal.

When the PSC_7 bit in the PSC register(2) is set to "1" (key input interrupt disabled), no key input interrupt

occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a

port pin is available even when in input mode.

NOTES:

2. Refer to 24. Programmable I/O Ports about the PSC register.

Figure 11.11 Key Input Interrupt

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