SH7046 datasheet(21/611 Pages) RENESAS

21 / 611 page

Rev. 4.00 Dec 05, 2005 page xxi of xliv

6.3.1

Interrupt Control Register 1 (ICR1).....................................................................

6.3.2

Interrupt Control Register 2 (ICR2).....................................................................

6.3.3

IRQ Status Register (ISR)....................................................................................

6.3.4

Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) ............................

6.4

Interrupt Sources ...............................................................................................................

6.4.1

External Interrupts ...............................................................................................

6.4.2

On-Chip Peripheral Module Interrupts ................................................................

6.4.3

User Break Interrupt ............................................................................................

6.5

Interrupt Exception Processing Vectors Table..................................................................

6.6

Interrupt Operation............................................................................................................

6.6.1

Interrupt Sequence ...............................................................................................

6.6.2

Stack after Interrupt Exception Processing ..........................................................

6.7

Interrupt Response Time ...................................................................................................

6.8

Data Transfer with Interrupt Request Signals ...................................................................

6.8.1

Handling Interrupt Request Signals as Sources for DTC Activating

and CPU Interrupt ................................................................................................

6.8.2

Handling Interrupt Request Signals as Source for DTC Activating,

but Not CPU Interrupt..........................................................................................

6.8.3

Handling Interrupt Request Signals as Source for CPU Interrupt

but Not DTC Activating.......................................................................................

Section 7 User Break Controller (UBC) ....................................................................... 91

7.1

Overview...........................................................................................................................

7.2

Register Descriptions ........................................................................................................93

7.2.1

User Break Address Register (UBAR) ................................................................

7.2.2

User Break Address Mask Register (UBAMR) ...................................................

7.2.3

User Break Bus Cycle Register (UBBR) .............................................................

7.2.4

User Break Control Register (UBCR)..................................................................

7.3

Operation ..........................................................................................................................

7.3.1

Flow of the User Break Operation .......................................................................

7.3.2

Break on On-Chip Memory Instruction Fetch Cycle ...........................................

7.3.3

Program Counter (PC) Values Saved...................................................................

7.4

Examples of Use ............................................................................................................... 100

7.5

Usage Notes ...................................................................................................................... 102

7.5.1

Simultaneous Fetching of Two Instructions ........................................................ 102

7.5.2

Instruction Fetches at Branches ........................................................................... 102

7.5.3

Contention between User Break and Exception Processing ................................ 103

7.5.4

Break at Non-Delay Branch Instruction Jump Destination.................................. 103

7.5.5

User Break Trigger Output .................................................................................. 103

7.5.6

Module Standby Mode Setting ............................................................................ 104

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