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SH7046 датащи(PDF) 39 Page - Renesas Technology Corp |
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SH7046 датащи(HTML) 39 Page - Renesas Technology Corp |
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39 / 611 page ![]() Rev. 4.00 Dec 05, 2005 page xxxix of xliv Tables Section 2 CPU Table 2.1 Initial Values of Registers ...................................................................................... 12 Table 2.2 Sign Extension of Word Data................................................................................. 14 Table 2.3 Delayed Branch Instructions .................................................................................. 15 Table 2.4 T Bit ....................................................................................................................... 15 Table 2.5 Immediate Data Accessing ..................................................................................... 16 Table 2.6 Absolute Address Accessing .................................................................................. 16 Table 2.7 Displacement Accessing......................................................................................... 17 Table 2.8 Addressing Modes and Effective Addresses .......................................................... 17 Table 2.9 Instruction Formats ................................................................................................ 21 Table 2.10 Classification of Instructions.................................................................................. 24 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes ................................................................................ 39 Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode............................... 40 Table 3.3 Operating Mode Pin Configuration ........................................................................ 40 Section 4 Clock Pulse Generator Table 4.1 Damping Resistance Values ................................................................................... 48 Table 4.2 Crystal Resonator Characteristics........................................................................... 48 Section 5 Exception Processing Table 5.1 Types of Exception Processing and Priority........................................................... 53 Table 5.2 Timing for Exception Source Detection and Start of Exception Processing .......... 54 Table 5.3 Exception Processing Vector Table........................................................................ 55 Table 5.4 Calculating Exception Processing Vector Table Addresses ................................... 56 Table 5.5 Reset Status ............................................................................................................ 57 Table 5.6 Bus Cycles and Address Errors .............................................................................. 59 Table 5.7 Interrupt Sources .................................................................................................... 60 Table 5.8 Interrupt Priority.....................................................................................................61 Table 5.9 Types of Exceptions Triggered by Instructions...................................................... 62 Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction.......................................................... 64 Table 5.11 Stack Status after Exception Processing Ends........................................................ 65 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration ................................................................................................... 69 Table 6.2 Interrupt Exception Processing Vectors and Priorities ........................................... 80 |
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