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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M32C/8B датащи(PDF) 229 Page - Renesas Technology Corp |
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M32C/8B датащи(HTML) 229 Page - Renesas Technology Corp |
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229 / 406 page  Under development M32C/8B Group 17. Serial Interfaces Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 212 of 385 17.1.1.1 CLK Polarity As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial clock. Figure 17.14 Serial Clock Polarity CLKi (1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock ) D0 D1 D3 D4 D5 D6 D7 D2 D0 D1 D3 D4 D5 D6 D7 D2 D0 D1 D3 D4 D5 D6 D7 D2 D0 D1 D3 D4 D5 D6 D7 D2 (2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock) TXDi RXDi The above applies under the following conditions: - UFORM bit in the UiC0 register is set to 0 (LSB first) - UiLCH bit in the UiC1 register is set to 0 (not inverted). NOTES: 1. The CLKi pin output level is "H" when no transmit and receive operation is in progress. 2. The CLKi pin output level is "L" when no transmit and receive operation is in progress. "H" "L" "H" "L" "H" "L" CLKi TXDi RXDi "H" "L" "H" "L" "H" "L" (note 1) (note 2) |
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