M32CSLASH8B datasheet(226/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 209 of 385

Figure 17.11

i = 0 to 4

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

2. The UiRRM bit can be set to 1 (continuous receive mode enabled), only when the CKDIR bit in the UiMR register is set to 1

(external clock) and RTS function is disabled.

Clock synchronous mode

Clock select bit

UiBRG register count source select bits

CTS function select bit

CTS function disable bit

Data output select bit

CLK polarity select bit

Bit order select bit

m = 00h to FFh

Baud rate =

Transmit operation disabled

Receive operation disabled

UARTi transmit interrupt source select bit

Continuous receive mode enable bit(2)

Data logic select bit

2(m + 1)

fj: f1, f8, f2n(1)

When an internal clock is used

Transmit/receive operation starts by writing data to the UiTB register.

Read the UiRB register when a receive operation is completed.

Start

End

UiMR register: bits SMD2 to SMD0 = 001b

CKDIR bit

bits 7 to 4 = 0000b

UiSMR register = 00h

UiSMR2 register = 00h

UiSMR3 register = 00h

UiSMR4 register = 00h

UiC0 register: bits CLK1 and CLK0

CRS bit

CRD bit

NCH bit

CKPOL bit

UFORM bit

UiBRG register = m

UiC1 register: TE bit = 0

RE bit = 0

UiIRS bit

UiRRM bit

UiLCH bit

Bit 7 = 0

Pin settings in the Function Select Registers

Transmit operation enabled

Receive operation enabled

UiC1 register: TE bit = 1

RE bit = 1

Transmit interrupt priority level select bit

Interrupt not requested

SiTIC register: bits ILVL2 to ILVL0

IR bit = 0

Receive interrupt priority level select bit

Interrupt not requested

SiRIC register: bits ILVL2 to ILVL0

IR bit= 0

Interrupt enabled

I flag = 1

Interrupt disabled

I flag = 0

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