AFE5804 datasheet(32/60 Pages) TI

32 / 60 page

SUMMARY OF FEATURES

AFE5804

SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com

Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued)

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

DEFAULT

GAIN_CH4<3:0>

Programmable gain channel 4.

0dB gain

GAIN_CH3<3:0>

Programmable gain channel 3.

0dB gain

GAIN_CH2<3:0>

Programmable gain channel 2.

0dB gain

GAIN_CH1<3:0>

Programmable gain channel 1.

0dB gain

GAIN_CH5<3:0>

Programmable gain channel 5.

0dB gain

GAIN_CH6<3:0>

Programmable gain channel 6.

0dB gain

GAIN_CH7<3:0>

Programmable gain channel 7.

0dB gain

GAIN_CH8<3:0>

Programmable gain channel 8.

0dB gain

Single-

DIFF_CLK

Differential clock mode.

ended clock

Enables the duty-cycle

EN_DCC

Disabled

correction circuit.

External

Drives the external reference

reference

EXT_REF_VCM

mode through the VCM pin.

drives REFT

and REFB

Controls the phase of LCLK

PHASE_DDR<1:0>

90 degrees

output relative to data.

PAT_DESKEW

Enables deskew pattern mode.

Inactive

PAT_SYNC

Enables sync pattern mode.

Inactive

Binary two's complement

Straight

BTC_MODE

format for ADC output.

offset binary

Serialized ADC output comes

LSB-first

MSB_FIRST

out MSB-first.

output

Enables SDR output mode

DDR output

EN_SDR

(LCLK becomes a 12x input

mode

clock).

Controls whether the LCLK

Rising edge

rising or falling edge comes in

of LCLK in

FALL_SDR

the middle of the data window

middle of

when operating in SDR output

data window

mode.

POWER IMPACT (Relative to Default)

FEATURES

DEFAULT

SELECTION

AT fS = 50MSPS

ANALOG FEATURES

Internal or external reference

Internal reference mode takes approximately 20mW more

N/A

(driven on the REFT and REFB pins)

power on AVDD1

External reference driven on the VCM pin

Off

Approximately 8mW less power on AVDD1

Duty cycle correction circuit

Off

Approximately 7mW more power on AVDD1

With zero input to the ADC, low-frequency noise suppression

Low-frequency noise suppression

Off

causes digital switching at fS/2, thereby increasing LVDD power

by approximately 5.5mW/channel

Differential clock mode takes approximately 7mW more power

Single-ended or differential clock

Single-ended

on AVDD1

Refer to the Power-Down Modes section in the Electrical

Power-down mode

Off

Pin and register 0F

Characteristics table

DIGITAL FEATURES

Programmable digital gain (0dB to 12dB)

0dB

Registers 2A and 2B

No difference

Straight offset or BTC output

Straight offset

No difference

Swap polarity of analog input pins

Off

No difference

LVDS OUTPUT PHYSICAL LAYER

LVDS internal termination

Off

Approximately 7mW more power on AVDD

LVDS current programmability

3.5mA

As per LVDS clock and data buffer current setting

LVDS OUTPUT TIMING

LSB- or MSB-first output

LSB-first

No difference

SDR mode takes approximately 2mW more power on LVDD

DDR or SDR output

DDR

(at fS = 30MSPS)

LCLK phase relative to data output

Refer to Figure 92

No difference

Submit Documentation Feedback

Product Folder Link(s): AFE5804

AFE5804 датащи(PDF) 32 Page - Texas Instruments

AFE5804 датащи(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

датащи скачать

ссылки URL