AFE5804 datasheet(37/60 Pages) TI

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POWER-DOWN MODES

AFE5804

www.ti.com ................................................................................................................................................ SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

NAME

PDN_CH<1:4>

PDN_CH<8:5>

PDN_PARTIAL

PDN_COMPLETE

PDN_PIN_CFG

Each of the eight ADC channels can be individually powered down. PDN_CH<N> controls the power-down mode

for the ADC channel <N>.

In addition to channel-specific power-down, the AFE5804 also has two global power-down modes: partial

power-down mode and complete power-down mode.

In addition to programming the device for either of these two power-down modes (through either the

PDN_PARTIAL or PDN_COMPLETE bits, respectively), the ADS_PD pin itself can be configured as either a

partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when

the ADS_PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when

the ADS_PD pin is high, the device enters partial power-down mode.

The partial power-down mode function allows the AFE5804 to be rapidly placed in a low-power state. In this

mode, most amplifiers in the signal path are powered down, while the internal references remain active. This

configuration ensures that the external bypass capacitors retain the respective charges, minimizing the wake-up

response time. The wake-up response is typically less than 50

µs, provided that the clock has been running for at

least 50

µs before normal operating mode resumes. The power-down time is instantaneous (less than 1.0µs).

In partial power-down mode, the part typically dissipates only 95mW, representing a 76% power reduction

compared to the normal operating mode. This function is controlled through the ADS_PD and VCA_PD pins,

which are designed to interface with 3.3V low-voltage logic. If separate control of the two PD pins is not desired,

then both can be tied together. In this case, the ADS_PD pin should be configured to operate as a partial

power-down mode pin (see below).

For normal operation the PD pins should be tied to a logic low (0); a high (1) places the AFE5804 into partial

power-down mode.

To achieve the lowest power dissipation of only 52mW, the AFE5804 can be placed in complete power-down

mode. This mode is controlled through the serial interface by setting Register 16 (bit D2) and Register 0F (bit

D9:D10). In complete power-down mode, all circuits (including references) within the AFE5804 are

powered-down, and the bypass capacitors then discharge. Consequently, the wake-up time from complete

power-down mode depends largely on the time needed to recharge the bypass capacitors. Another factor that

affects the wake-up time is the elapsed time that the AFE5804 spends in shutdown mode.

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