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HD6417618A датащи(PDF) 337 Page - Renesas Technology Corp |
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HD6417618A датащи(HTML) 337 Page - Renesas Technology Corp |
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337 / 646 page ![]() Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 6.00 Jun. 12, 2007 Page 305 of 610 REJ09B0131-0600 Yes Yes Yes Yes Yes Next transmission task generated? TACT = 0? 1. 2. 3. 4. 4. 5. 6. No No No No Yes No No Prepare multiple transmit descriptors. Transmission starts. Transmission task Interrupt handler TC interrupt? Interrupt other than TC? Save EESR and clear the bit by writing a 1. Generation of EtherC/E-DMAC interrupt End End After setting the transmit descriptor, set the TR bit in EDTRR to 1. Read the TACT bit of the corresponding transmit descriptor. After setting the corresponding transmit descriptor, set the TR bit in EDTRR to 1. Has the transmission task left the waiting state within the specified time? Place the transmission task in a waiting state by calling an OS service routine with a timeout function. Make an OS service call to bring the transmission task out of the waiting state. Interrupt processing for interrupts other than TC Read the TACT bit of the corresponding transmit descriptor. TACT = 0? TC: EESR frame transmission complete : Processing added as the countermeasure for the problem Timeout Figure 12.10 Method of Adding Timeout Processing |
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