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HD6417618A датащи(PDF) 335 Page - Renesas Technology Corp

номер детали HD6417618A
подробное описание детали  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618A датащи(HTML) 335 Page - Renesas Technology Corp

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 6.00 Jun. 12, 2007 Page 303 of 610
REJ09B0131-0600
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Next transmission task
generated?
TACT = 0?
1.
2.
3.
4.
5.
7.
5.
6.
No
No
No
No
No
No
No
Prepare multiple transmit descriptors.
Prepare the condition flag and turn it off.
Transmission starts
Transmission task
Interrupt handler
TC interrupt?
Interrupt other than TC?
TC: EESR frame transmission complete
: Processing added as the countermeasure for the problem
Is the condition flag on?
Save EESR and clear the bit
by writing a 1.
Turn off the condition flag.
Generation of EtherC/E-DMAC
interrupt
End
End
After setting the transmit
descriptor, set the TR bit in EDTRR to 1.
Read the TACT bit of the
corresponding transmit descriptor.
After setting the corresponding transmit
descriptor, set the TR bit in EDTRR to 1.
Has the transmission task
been brought out of the waiting state
by the interrupt handler?
Turn the condition flag on.
Make an OS service call to place
the transmission task in a waiting state.
Make an OS service call to bring the
transmission task out of the waiting state.
Make an OS service call to bring the
transmission task out of the waiting state.
Read the TACT bit of the corresponding
transmit descriptor.
Interrupt processing for interrupts
other than TC
TACT = 0?
Figure 12.9 Countermeasure by Monitoring the Transmit Descriptor in Processing of
Interrupts Other than the Frame Transmit Complete (TC) Interrupt



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