SH7201 datasheet(22/1196 Pages) RENESAS

22 / 1196 page

Rev. 2.00 Sep. 07, 2007 Page xxii of xxviii

17.6

Bit Synchronous Circuit..................................................................................................... 763

17.7

Usage Note......................................................................................................................... 766

17.7.1 Issuance of Stop Condition and Start Condition (Retransmission)....................... 766

17.7.2 Settings for Multi-Master Operation..................................................................... 766

17.7.3 Reading ICDRR in Master Receive Mode............................................................ 766

Section 18 Serial Sound Interface (SSI) ............................................................ 767

18.1

Features.............................................................................................................................. 767

18.2

Input/Output Pins...............................................................................................................769

18.3

Register Description .......................................................................................................... 770

18.3.1 Control Register (SSICR) ..................................................................................... 771

18.3.2 Status Register (SSISR) ........................................................................................ 777

18.3.3 Transmit Data Register (SSITDR)........................................................................ 782

18.3.4 Receive Data Register (SSIRDR) ......................................................................... 782

18.4

Operation Description........................................................................................................ 783

18.4.1 Bus Format ........................................................................................................... 783

18.4.2 Non-Compressed Modes....................................................................................... 784

18.4.3 Operation Modes .................................................................................................. 794

18.4.4 Transmit Operation ............................................................................................... 795

18.4.5 Receive Operation ................................................................................................ 798

18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 801

18.4.7 Serial Bit Clock Control ....................................................................................... 802

18.5

Usage Notes ....................................................................................................................... 802

18.5.1 Limitations from Overflow during Receive DMA Operation............................... 802

18.5.2 Note on Using Oversample Clock ........................................................................ 803

18.5.3 Restriction on Stopping Clock Supply.................................................................. 803

Section 19 Controller Area Network (RCAN-ET) ............................................ 805

19.1

Summary............................................................................................................................ 805

19.1.1 Overview .............................................................................................................. 805

19.1.2 Scope .................................................................................................................... 805

19.1.3 Audience............................................................................................................... 805

19.1.4 References ............................................................................................................ 806

19.1.5 Features................................................................................................................. 806

19.2

Architecture ....................................................................................................................... 807

19.2.1 Block Diagram...................................................................................................... 807

19.2.2 Functions of Each Block....................................................................................... 808

19.2.3 Input/Output Pins.................................................................................................. 809

19.2.4 Memory Map ........................................................................................................ 810

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