SH7147 datasheet(28/1108 Pages) RENESAS

28 / 1108 page

Section 1 Overview

Rev. 3.00 Oct. 06, 2008 Page 4 of 1080

REJ09B0230-0300

Items

Specification

On-chip ROM

• 256 Kbytes/384 Kbytes/512 Kbytes (see the list in product lineup)

On-chip RAM

• 12 Kbytes/16 Kbytes (see the list in product lineup)

Bus state controller

(BSC)

• Address space: A maximum 64 Mbytes for each of two areas (CS0 and

CS1)

• 8-bit external bus

• The following features settable for each area independently

⎯ Number of access wait cycles

⎯ Idle wait cycle insertion

⎯ Supports SRAM

• Outputs a chip select signal according to the target area

Data transfer

controller (DTC)

• Data transfer activated by an on-chip peripheral module interrupt can

be done independently of the CPU transfer.

• Transfer mode selectable for each interrupt source (transfer mode is

specified in memory)

• Multiple data transfer enabled for one activation source

• Various transfer modes

Normal mode, repeat mode, or block transfer mode can be selected.

• Data transfer size can be specified as byte, word, or longword

• The interrupt that activated the DTC can be issued to the CPU.

A CPU interrupt can be requested after one data transfer completion.

• A CPU interrupt can be requested after all specified data transfer

completion.

Interrupt controller

(INTC)

• Five external interrupt pins (NMI and IRQ3 to IRQ0)

• On-chip peripheral interrupts: Priority level set for each module

• Vector addresses: A vector address for each interrupt source

SH7147 датащи(PDF) 28 Page - Renesas Technology Corp