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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7147 датащи(PDF) 86 Page - Renesas Technology Corp |
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SH7147 датащи(HTML) 86 Page - Renesas Technology Corp |
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86 / 1108 page  Section 4 Clock Pulse Generator (CPG) Rev. 3.00 Oct. 06, 2008 Page 62 of 1080 REJ09B0230-0300 4.3 Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Clock I/O Clock Operating Mode Source Output PLL Circuit Input to Divider 1 EXTAL input or crystal resonator CK* ON ( ×8) ×8 Note: * To output the clock through the clock output (CK) pin, appropriate settings should be made in the pin function controller (PFC). For details, refer to section 18, Pin Function Controller (PFC). Mode 1: The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 8 MHz to 10 MHz can be used, the internal clock (I φ) frequency ranges from 10 MHz to 80 MHz. Maximum operating frequencies: I φ = 80 MHz, Bφ = 40 MHz, Pφ = 40 MHz, MIφ = 80 MHz, and MPφ = 40 MHz (T opr = -40 to +85°C) Maximum operating frequencies: I φ = 64 MHz, Bφ = 32 MHz, Pφ = 32 MHz, MIφ = 64 MHz, and MPφ = 32 MHz (T opr = −40 to +125°C) Table 4.4 shows the frequency division ratios that can be specified with FRQCR. |
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