M37274EFSP datasheet(59/148 Pages) RENESAS

59 / 148 page

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274EFSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

(5) I2C Status Register

The I2C status register (address 00F816) controls the I2C-BUS inter-

face status. The low-order 4 bits are read-only bits and the high-

order 4 bits can be read out and written to.

s Bit 0: Last Receive Bit (LRB)

This bit stores the last bit value of received data and can also be

used for ACK receive confirmation. If ACK is returned when an ACK

clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit

is set to “1.” Except in the ACK mode, the last bit value of received

data is input. The state of this bit is changed from “1” to “0” by execut-

ing a write instruction to the I2C data shift register (address 00F616).

s Bit 1: General Call Detecting Flag (AD0)

This bit is set to “1” when a general callV whose address data is all “0”

is received in the slave mode. By a general call of the master device,

every slave device receives control data after the general call. The

AD0 bit is set to “0” by detecting the STOP condition or START con-

dition.

VGeneral call: The master transmits the general call address “0016”

to all slaves.

s Bit 2: Slave Address Comparison Flag (AAS)

This flag indicates a comparison result of address data.

In the slave receive mode, when the 7-bit addressing format is

selected, this bit is set to “1” in one of the following conditions.

•The address data immediately after occurrence of a START

condition matches the slave address stored in the high-order

7 bits of the I2C address register (address 00F716).

•A general call is received.

In the slave reception mode, when the 10-bit addressing format is

selected, this bit is set to “1” with the following condition.

•When the address data is compared with the I2C address

bytes match.

The state of this bit is changed from “1” to “0” by executing a write

instruction to the I2C data shift register (address 00F616). s Bit 3:

Arbitration LostV Detecting Flag (AL)

In the master transmission mode, when a device other than the mi-

crocomputer sets the SDA to “L,”, arbitration is judged to have been

lost, so that this bit is set to “1.” At the same time, the TRX bit is set to

“0,” so that immediately after transmission of the byte whose arbitra-

tion was lost is completed, the MST bit is set to “0.” When arbitration

is lost during slave address transmission, the TRX bit is set to “0”

and the reception mode is set. Consequently, it becomes possible to

receive and recognize its own slave address transmitted by another

master device.

VArbitration lost: The status in which communication as a master is

disabled.

s Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN)

This bit generates an interrupt request signal. Each time 1-byte data

is transmitted, the state of the PIN bit changes from “1” to “0.” At the

same time, an interrupt request signal is sent to the CPU. The PIN bit

is set to “0” in synchronization with a falling edge of the last clock

(including the ACK clock) of an internal clock and an interrupt re-

quest signal occurs in synchronization with a falling edge of the PIN

bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock

generation is disabled. Figure 57 shows an interrupt request signal

generating timing chart.

The PIN bit is set to “1” in any one of the following conditions.

•Executing a write instruction to the I2C data shift register (address

00F616).

•When the ESO bit is “0”

•At reset

The conditions in which the PIN bit is set to “0” are shown below:

•Immediately after completion of 1-byte data transmission (includ-

ing when arbitration lost is detected)

•Immediately after completion of 1-byte data reception

•In the slave reception mode, with ALS = “0” and immediately after

completion of slave address or general call address reception

•In the slave reception mode, with ALS = “1” and immediately after

completion of address data reception

s Bit 5: Bus Busy Flag (BB)

This bit indicates the status of use of the bus system. When this bit is

set to “0,” this bus system is not busy and a START condition can be

generated. When this bit is set to “1,” this bus system is busy and the

occurrence of a START condition is disabled by the START condi-

tion duplication prevention function (Note).

This flag can be written by software only in the master transmission

mode. In the other modes, this bit is set to “1” by detecting a START

condition and set to “0” by detecting a STOP condition. When the

ESO bit of the I2C control register (address 00F916) is “0” and at

reset, the BB flag is kept in the “0” state.

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