7546 datasheet(59/95 Pages) RENESAS

59 / 95 page

Rev.1.21

Nov 15, 2006

page 59 of 93

REJ03B0160-0121

7546 Group

(1) Oscillation control

• Stop mode

When the STP instruction is executed, the internal clock

φ stops at

an “H” level and the XIN oscillator stops. At this time, timer 1 is set

to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-

bilization time set bit after release of the STP instruction is “0”. On

the other hand, timer 1 and prescaler 1 are not set when the

above bit is “1”. Accordingly, set the wait time fit for the oscillation

stabilization time of the oscillator to be used. f(XIN)/16 is forcibly

connected to the input of prescaler 1. When an external interrupt

is accepted, oscillation is restarted but the internal clock

φ remains

at “H” until timer 1 underflows. As soon as timer 1 underflows, the

internal clock

φ is supplied. This is because when a ceramic oscil-

lator is used, some time is required until a start of oscillation. In

case oscillation is restarted by reset, no wait time is generated. So

apply an “L” level to the RESET pin while oscillation becomes

stable, or set the wait time by on-chip oscillator operation after

system is released from reset until the oscillation is stabled.

• Wait mode

If the WIT instruction is executed, the internal clock

φ stops at an

“H” level, but the oscillator does not stop. The internal clock re-

starts if a reset occurs or when an interrupt is received. Since the

oscillator does not stop, normal operation can be started immedi-

ately after the clock is restarted. To ensure that interrupts will be

received to release the STP or WIT state, interrupt enable bits

must be set to “1” before the STP or WIT instruction is executed.

Fig. 74 Structure of CPU mode register

Oscillation mode selection bit (Note 1, Note 4)

0 : Ceramic oscillation

1 : RC oscillation

CPU mode register (Note 1)

(CPUM: address 003B16, initial value: 8016)

Stack page selection bit

0 : 0 page

1 : 1 page

Clock division ratio selection bits

b7 b6

0 : f(

φ) = f(XIN)/2 (High-speed mode)

1 : f(

φ) = f(XIN)/8 (Middle-speed mode)

0 : applied from on-chip oscillator

1 : f(

φ) = f(XIN)/1 (Double-speed mode)(Note 5)

On-chip oscillator oscillation control bit (Note 3)

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

XIN oscillation control bit

0 : Ceramic or RC oscillation enabled

1 : Ceramic or RC oscillation stop

Processor mode bits

b1 b0

0 Single-chip mode

1 Not available

0 Not available

1 Not available

Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed

after releasing reset since bit 5 of CPUM is fixed.

2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0).

The setting values of FSROM2 are invalid by setting “1” to this bit.

(In order that FSROM2 is invalid, write to CPUM after releasing reset.)

3: When bit 4 of FSROM2 is set to “0”, the operation of on-chip oscillator cannot be stopped.

Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased.

4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2.

Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset.

After rewriting it is disable to write any data to this bit.

This bit is initialized by reset, and then, rewriting it is enabled.

5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation.

Control by Function set ROM data 2

(FSROM2: address FFDA16) (Note 2)

This bit function can be set by setting bit 5 of FSROM2. (Note 4)

Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to “0”.

Bit 5 of FSROM2 = 1: Bit 5 of CPUM is “0” or “1”.

This cannot be controlled by FSROM2.

This bit function can be set by setting bit 4 of FSROM2. (Note 3)

Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to “0”.

Bit 4 of FSROM2 = 1: Bit 3 of CPUM is “0” or “1”.

This cannot be controlled by FSROM2.

s Notes on Clock Generating Circuit

For use with the oscillation stabilization set bit after release of the

STP instruction set to “1”, set values in timer 1 and prescaler 1 af-

ter fully appreciating the oscillation stabilization time of the

oscillator to be used.

• Switch of ceramic and RC oscillations

After releasing reset the operation starts by starting an on-chip os-

cillator. Then, a ceramic oscillation or an RC oscillation is selected

by setting bit 5 of the CPU mode register.

• Double-speed mode

When a ceramic oscillation is selected, a double-speed mode can

be used. Do not use it when an RC oscillation is selected.

• CPU mode register

Bits 5, 1 and 0 of CPU mode register are used to select oscillation

mode and to control operation modes of the microcomputer. In or-

der to prevent the dead-lock by error-writing (ex. program

run-away), these bits can be rewritten only once after releasing re-

set. After rewriting it is disable to write any data to the bit. (The

emulator MCU “M37542RSS” is excluded.)

Also, when the read-modify-write instructions (SEB, CLB) are ex-

ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.

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