7546 datasheet(39/95 Pages) RENESAS

39 / 95 page

Rev.1.21

Nov 15, 2006

page 39 of 93

REJ03B0160-0121

7546 Group

Input capture

7546 group has 2-input capture channels. Each channel (0 and 1)

has the same function and can be used to capture count value of

either Timer A or Timer B.

The source timer for each channel is selected by setting value of

the capture x (x = 0, 1) timer source bit. Timer A and Timer B can

be selected for the source timer to each channel, respectively.

To use each capture channel, set the capture x input port bits and

set the port direction register corresponding to capture channel to

input mode.

The input capture circuit retains the count value of selected timer

when external trigger is input. The timer count value is retained to

the capture latch x0 when rising edge is input and is retained to

the capture latch x1 when falling edge is input.

The count value of timer can be retained by software by capture y

(y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this

bit, count value of timer is retained to the corresponded capture

latch.

When reading from the capture y software trigger bit is executed,

“0” is read out.

The latest status of capture latch can be confirmed by reading of

the capture x status bit. This bit indicates the capture latch which

latest data is in.

The valid trigger edge for capture interrupt is set by the capture x

interrupt edge selection bits. (Regardless of the setting value of

capture x interrupt edge selection bits, timer count values for both

edges are retained to the capture latch.)

Each capture input has the noise filter circuit that judges continu-

ous 4-time same level with sampling clock to be valid. The

sampling clock of noise filter is set by the capture x noise filter

clock selection bits.

Reading from the register for each channel is controlled by setting

value of the capture register read pointer. Reading from each reg-

ister is in the following order;

1.Set the value of the corresponded input capture channel to the

capture register read pointer.

2.Read from the capture register (low-order) and capture register

(high-order).

s Notes on Input Capture

• If the capture trigger is input while the capture register (low-order

and high-order) is in read, captured value is changed between

high-order reading and low-order reading. Accordingly, some

countermeasure by program is recommended, for example

comparing the values that twice of read.

• When CPU operation clock source is XIN oscillation and the on-

chip-oscillator is selected for Timer A count source, Timer A

cannot be used for the capture source timer.

Timer B cannot be used for the capture source timer when the

system is in the following state;

• CPU operation clock source: XIN oscillation

• Timer B count source: Timer A underflow

• Timer A count source: On-chip oscillator output

• When writing “1” to capture latch x0 (x1) software trigger bit of

capture latch x0 and x1 at the same time, or external trigger and

software trigger occur simultaneously, the set value of capture x

status bit is undefined.

• When setting the interrupt active edge selection bit and noise fil-

ter clock selection bit of external interrupt CAP0, CAP1, the

interrupt request bit may be set to “1”.

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

➀ Set the corresponding interrupt enable bit to “0” (disabled).

➁ Set the interrupt edge selection bit or noise filter clock selection bit.

➂ Set the corresponding interrupt request bit to “0” after 1 or more

instructions have been executed.

➃ Set the corresponding interrupt enable bit to “1” (enabled).

• When the capture interrupt is used as the interrupt for return

from stop mode, set the capture x noise filter clock selection bits

to “00 (Filter stop)”.

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