4524 datasheet(29/161 Pages) RENESAS

29 / 161 page

Rev.2.00

Jul 27, 2004

page 29 of 159

REJ03B0091-0200Z

4524 Group

(4) Notes on External 0 interrupts

➀ Note [1] on bit 3 of register I1

When the input of the INT0 pin is controlled with the bit 3 of reg-

ister I1 in software, be careful about the following notes.

• Depending on the input state of the D8/INT0 pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 3 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)

and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

to “0” after executing at least one instruction (refer to Figure

18➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 18➂).

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (1✕✕✕2)

TI1A

; Control of INT0 pin input is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 18 External 0 interrupt program example-1

➁ Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared, the power down function

is selected and the input of INT0 pin is disabled, be careful about

the following notes.

• When the input of INT0 pin is disabled, invalidate the key-on

wakeup function of INT0 pin (register K20 = “0”) before system

goes into the power down mode. (refer to Figure 19➀).

; (✕✕✕02)

TK2A

; INT0 key-on wakeup invalid ........... ➀

EPOF

POF2

; RAM back-up

✕ : these bits are not used here.

Fig. 19 External 0 interrupt program example-2

➂ Note on bit 2 of register I1

When the interrupt valid waveform of the D8/INT0 pin is changed

with the bit 2 of register I1 in software, be careful about the fol-

lowing notes.

• Depending on the input state of the D8/INT0 pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 2 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)

and then, change the bit 2 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

to “0” after executing at least one instruction (refer to Figure

20➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 20➂).

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (✕1✕✕2)

TI1A

; Interrupt valid waveform is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 20 External 0 interrupt program example-3

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