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4524 датащи(PDF) 49 Page - Renesas Technology Corp |
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4524 датащи(HTML) 49 Page - Renesas Technology Corp |
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49 / 161 page ![]() Rev.2.00 Jul 27, 2004 page 49 of 159 REJ03B0091-0200Z 4524 Group Fig. 35 Setting registers A/D control register Q2 AIN4 pin function selected ✕✕✕ 1 (Bit 3) (Bit 0) (7) A/D conversion timing chart Figure 34 shows the A/D conversion timing chart. Fig. 34 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P30/AIN4 pin is A/D converted, and the high- order 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. ➀ Select the AIN4 pin function with the bit 0 of the register Q3. Se- lect the AIN4 pin function and A/D conversion mode with the register Q1 (refer to Figure 35). ➁ Execute the ADST instruction and start A/D conversion. ➂ Examine the state of ADF flag with the SNZAD instruction to de- termine the end of A/D conversion. ➃ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ➅ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ➇ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). ADST instruction A/D conversion completion flag (ADF) 62 machine cycles DAC operation signal A/D control register Q1 AIN4 pin selected A/D conversion mode 010 0 (Bit 3) (Bit 0) ✕: Set an arbitrary value. |
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