4518 datasheet(59/160 Pages) RENESAS

59 / 160 page

Rev.3.01

2005.06.15

page 59 of 157

REJ03B0008-0301

4518 Group

• Program counter (PC) ..........................................................................................................

Address 0 in page 0 is set to program counter.

• Interrupt enable flag (INTE) ..................................................................................................

• Power down flag (P) .............................................................................................................

• External 0 interrupt request flag (EXF0) ..............................................................................

• External 1 interrupt request flag (EXF1) ..............................................................................

• Interrupt control register V1 ..................................................................................................

• Interrupt control register V2 ..................................................................................................

• Interrupt control register I1 ...................................................................................................

• Interrupt control register I2 ...................................................................................................

• Timer 1 interrupt request flag (T1F) .....................................................................................

• Timer 2 interrupt request flag (T2F) .....................................................................................

• Timer 3 interrupt request flag (T3F) .....................................................................................

• Timer 4 interrupt request flag (T4F) .....................................................................................

• Watchdog timer flags (WDF1, WDF2) ..................................................................................

• Watchdog timer enable flag (WEF) ......................................................................................

• Timer control register PA ......................................................................................................

• Timer control register W1 .....................................................................................................

• Timer control register W2 .....................................................................................................

• Timer control register W3 .....................................................................................................

• Timer control register W4 .....................................................................................................

• Timer control register W5 .....................................................................................................

• Timer control register W6 .....................................................................................................

• Clock control register MR .....................................................................................................

• Clock control register RG .....................................................................................................

• Serial I/O transmit/receive completion flag (SIOF) ..............................................................

• Serial I/O mode register J1 ..................................................................................................

• Serial I/O register SI .............................................................................................................

• A/D conversion completion flag (ADF) .................................................................................

• A/D control register Q1 .........................................................................................................

• A/D control register Q2 .........................................................................................................

• A/D control register Q3 .........................................................................................................

• Successive comparison register AD ....................................................................................

• Comparator register ..............................................................................................................

• Key-on wakeup control register K0 ......................................................................................

• Key-on wakeup control register K1 ......................................................................................

• Key-on wakeup control register K2 ......................................................................................

• Pull-up control register PU0 .................................................................................................

• Pull-up control register PU1 .................................................................................................

“✕” represents undefined.

Fig. 49 Internal state at reset 1

(2) Internal state at reset

Figure 49 and 50 show internal state at reset (they are the same af-

ter system is released from reset). The contents of timers, registers,

flags and RAM except shown in Figure are undefined, so set the

initial value to them.

000

0000

000

(Interrupt disabled)

(Prescaler stopped)

(Timer 1 stopped)

(Timer 2 stopped)

(Timer 3 stopped)

(Timer 4 stopped)

00(Period measurement circuit stopped)

(On-chip oscillator operating)

(External clock selected,

serial I/O port not selected)

✕✕✕

✕✕

✕✕✕

✕✕

✕✕✕

✕✕

✕✕✕

✕✕

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