4502 datasheet(21/116 Pages) RENESAS

21 / 116 page

4502 Group

Rev.3.01

2005.02.02

page 21 of 112

REJ03B0105-0301

Table 7 External interrupt activated conditions

Name

External 0 interrupt

Input pin

INT

Activated condition

When the next waveform is input to INT pin

• Falling waveform (“H”

→“L”)

• Rising waveform (“L”

→“H”)

• Both rising and falling waveforms

Valid waveform

selection bit

I11

I12

Fig. 17 External interrupt circuit structure

EXTERNAL INTERRUPTS

The 4502 Group has the external 0 interrupt. An external interrupt

request occurs when a valid waveform is input to an interrupt input

pin (edge detection).

The external interrupt can be controlled with the interrupt control

I12

EXF0

I11

SNZI0 instruction

P13/INT

K13

I13

(Note)

Wakeup

Skip

Rising

Falling

One-sided edge

detection circuit

Both edges

detection circuit

External 0

interrupt

This symbol represents a parasitic diode on the port.

•

Timer 1 count start

synchronization

circuit input

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a valid

waveform is input to INT pin.

The valid waveforms causing the interrupt must be retained at their

level for 4 clock cycles or more of the system clock (Refer to Figure

16).

The state of EXF0 flag can be examined with the skip instruction

(SNZ0). Use the interrupt control register V1 to select the interrupt

or the skip instruction. The EXF0 flag is cleared to “0” when an in-

terrupt occurs or when the next instruction is skipped with the skip

instruction.

• External 0 interrupt activated condition

External 0 interrupt activated condition is satisfied when a valid

waveform is input to INT pin.

The valid waveform can be selected from rising waveform, falling

waveform or both rising and falling waveforms. An example of

how to use the external 0 interrupt is as follows.

➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input

enabled state.

➁ Select the valid waveform with the bits 1 and 2 of register I1.

➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.

➃ Set the NOP instruction for the case when a skip is performed

with the SNZ0 instruction.

➄ Set both the external 0 interrupt enable bit (V10) and the INTE

flag to “1.”

The external 0 interrupt is now enabled. Now when a valid wave-

form is input to the INT pin, the EXF0 flag is set to “1” and the

external 0 interrupt occurs.

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