4502 datasheet(49/116 Pages) RENESAS

49 / 116 page

4502 Group

Rev.3.01

2005.02.02

page 49 of 112

REJ03B0105-0301

Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared to “0”, the RAM back-up

mode is selected and the input of INT pin is disabled, be careful

about the following notes.

• When the key-on wakeup function of port P13 is not used (regis-

ter K13 = “0”), clear bits 2 and 3 of register I1 before system

enters to the RAM back-up mode. (refer to Figure 50➀).

; (00✕✕2)

TI1A

; Input of INT disabled ........................ ➀

EPOF

POF

; RAM back-up

✕ : these bits are not used here.

Fig. 50 External 0 interrupt program example-2

Note [3] on bit 2 of register I1

When the interrupt valid waveform of the P13/INT pin is changed

with the bit 2 of register I1 in software, be careful about the fol-

lowing notes.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 2 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 51➀)

and then, change the bit 2 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag to

“0” after executing at least one instruction (refer to Figure 51➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 51➂).

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (✕1✕✕2)

TI1A

; Interrupt valid waveform is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 51 External 0 interrupt program example-3

; (✕✕✕02)

TV1A

; The SNZ0 instruction is valid ........... ➀

; (1✕✕✕2)

TI1A

; Control of INT pin input is changed

NOP

........................................................... ➁

SNZ0

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➂

✕ : these bits are not used here.

Fig. 49 External 0 interrupt program example-1

P13/INT pin

Note [1] on bit 3 of register I1

When the input of the INT pin is controlled with the bit 3 of regis-

ter I1 in software, be careful about the following notes.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 3 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 49➀)

and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag to

“0” after executing at least one instruction (refer to Figure 49➁).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 49➂).

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