3822 datasheet(13/59 Pages) RENESAS

13 / 59 page

Rev.1.20

Dec 24, 2003

page 13 of 57

3822 Group (A ver.)

Fig. 10 Memory map of special function register (SFR)

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

Port P0 (P0)

Port P1 (P1)

Port P1 output control register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

Serial I/O status register (SIOSTS)

Serial I/O control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Interrupt control register 2(ICON2)

Timer 3 (T3)

Timer X mode register (TXM)

Interrupt edge selection register

(INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1(IREQ1)

Interrupt request register 2(IREQ2)

Interrupt control register 1(ICON1)

Timer X (low) (TXL)

Timer Y (low) (TYL)

Timer 1 (T1)

Timer 2 (T2)

Timer X (high) (TXH)

Timer Y (high) (TYH)

PULL register A (PULLA)

PULL register B (PULLB)

Timer Y mode register (TYM)

Timer 123 mode register (T123M)

φ output control register (CKOUT)

Segment output enable register (SEG)

LCD mode register (LM)

A-D control register (ADCON)

A-D conversion register (AD)

Transmit/Receive buffer register (TB/RB)

Port P0 direction register (P0D)

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