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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD404849FS датащи(PDF) 23 Page - Renesas Technology Corp |
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HD404849FS датащи(HTML) 23 Page - Renesas Technology Corp |
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23 / 127 page  HD404849 Series 21 Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT 0 INT 1 Timer A Timer B or INT 2 Timer C or INT 3 Timer D A/D or Serial IE 11111 11 IF0 • IM0 10000 00 IF1 • IM1 * 1000 00 IFTA • IMTA ** 100 00 IFTB • IMTB + IF2 • IM2 *** 10 00 IFTC • IMTC + IF3 • IM3 **** 10 0 IFTD • IMTD ***** 10 IFAD • IMAD + IFS • IMS ***** * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 12 3 4 5 6 Instruction execution IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: * * Stacking The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Figure 10 Interrupt Processing Sequence |
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