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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD404849FS датащи(PDF) 59 Page - Renesas Technology Corp |
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HD404849FS датащи(HTML) 59 Page - Renesas Technology Corp |
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59 / 127 page  HD404849 Series 57 1/4 1/2 32.768-kHz oscillator System clock Prescaler W (PSW) Selector Selector Prescaler S (PSS) Timer A interrupt request flag (IFTA) Clock Overflow Timer counter A (TCA) Timer mode register A (TMA) 3 2 f 1/2 twcyc f twcyc ø PER W W Figure 40 Block Diagram of Timer A Timer A Operations: • Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. • Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. • Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 41. |
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