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HD151TS207SS датащи(PDF) 8 Page - Renesas Technology Corp

номер детали HD151TS207SS
подробное описание детали  Mother Board Clock Generator for Intel P4 Chipset (Springdale)
PDF  38 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD151TS207SS датащи(HTML) 8 Page - Renesas Technology Corp

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HD151TS207SS
Rev.1.00, Apr.25.2003, page 8 of 38
I
2C Controlled Register Bit Map (cont.)
Table3 FS_A and FS_B pin Input level
Logic Level
Min Voltage
Max Voltage
0 (Low)
0.35V
1 (High)
0.70V
Byte1 Control Register
Bit
Description
Contents
Type
Default
Note
7
Allow control of SCR with assertion
of PCI_STOP#
0 = Free running
1 = Stopped with
PCI_STOP#
RW
0
See
Table5
6
SRC Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
5
Reserved
RW
1
4
Reserved
RW
1
3
Reserved
RW
1
2
CPU2 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
1
CPU1 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
0
CPU0 Output enable
0 = Disabled (tristate)
1 = Enabled
RW
1
Byte2 Control Register
Bit
Description
Contents
Type
Default
Note
7
SRC_Pwrdwn drive mode
0 = Driven in power down,
1 = Tristate
RW
0
6
SRC_Stop drive mode
0 = Driven when stopped,
1 = Tristate
RW
0
See
Table5
5
CPU2_Pwrdwn drive mode
0 = Driven in power down,
1 = Tristate
RW
0
4
CPU1_Pwrdwn drive mode
0 = Driven in power down,
1 = Tristate
RW
0
3
CPU0_Pwrdwn drive mode
0 = Driven in power down,
1 = Tristate
RW
0
2
Reserved
RW
0
1
Reserved
RW
0
0
Reserved
RW
0
See
Table4



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