HD151TS207SS datasheet(5/38 Pages) RENESAS

5 / 38 page

HD151TS207SS

Rev.1.00, Apr.25.2003, page 5 of 38

Pin Descriptions (cont.)

Pin name

No.

Type

Description

PWRDWN#/

SAFE_F#

INPUT

PULL–UP*

PWRDWN# / SAFE_F# selectable input.

Default is PWRDWN# input.

Byte15[5] = “1” : SAFE_F# input.

PWRDWN# is all clocks stop pin.

Asynchronous active “Low” input.

When asserted low, all output clocks are disabled.

SAFE_F# is active “Low” input.

When SAFE_F# is “Low” ,frequency mode is changed to the

predefined frequency mode.

3V66_0/RESET#

OUTPUT

3V66 / Watchdog RESET# selectable output.

Default is 3V66 output.

This signal is active low and selected by Mode latch input.

3V66_[1:3]

23,26,

OUTPUT

3V66 clock 3.3V outputs.

SCLK

INPUT

PULL-UP*

Clock input for I

2C logic.

**SEL66_48/

3V66_4/VCH

INPUT/

OUTPUT

Latched select input for 3V66/VCH output 1 = 48 MHz,

0 = 66.66 MHz. /3V66 or VCH clock output.

SDATA

IN/OUTPUT

PULL-UP*

Data input for I

2C logic.

**SEL48_24/

USB_48

INPUT/

OUTPUT

Latched select input for 48_24 MHz output

1 = 24 MHz, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.

FS3/DOT_48

INPUT/

OUTPUT

Frequency select latch input pin.

/DOT_48 clock 3.3 V output.

VTT_PWRGD#

INPUT

PULL-UP*

Qualifying input that latches FS_A and FS_B.

When asserted low, FS_A and FS_B are latched.

SRC#

OUTPUT

“Complementary” clock of Differential Serial Reference Clock.

SRC

OUTPUT

“True” clock of Differential Serial Reference Clock.

CPU_[0:2]#

40,43,

OUTPUT

“Complementary” clock of differential CPU clock.

CPU_[0:2]

41,44,

OUTPUT

“True” clock of differential CPU clock.

PCI_STOP#

INPUT

PULL–UP*

PCI clocks stop pin. Active “Low” input.

When asserted low, PCI[6:0] and SRC clocks are

synchronously disabled in low state.

Usually this pin does not give to effect PCIF[2:0] clock outputs.

TEST_CLK#

INPUT

PULL-UP*

Test clock mode pin. Active “Low” input.

FS_[A:B]

51,52

INPUT

CPU clocks frequency select latch input.

IREF

INPUT

A precision resistor is attached to this pin which is connected

to internal current reference.

A resistor is connected between this pin and GNDIREF.

Note:

(*):

Those pins are 150 k

Ω internal pulled-UP.

(**):

Those pins are 150 k

Ω internal pulled-DOWN

HD151TS207SS датащи(PDF) 5 Page - Renesas Technology Corp

HD151TS207SS датащи(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

датащи скачать

ссылки URL