HD151TS201AT

Rev.1.00, Oct.21.2003, page 12 of 28

I

Byte10 PLL N Divide Ratio Control Register

Bit

Description

Contents

Default

7

PLL N Divider Control bit7

PLL N Divider Control bit7

X

6

PLL N Divider Control bit6

PLL N Divider Control bit6

X

5

PLL N Divider Control bit5

PLL N Divider Control bit5

X

4

PLL N Divider Control bit4

PLL N Divider Control bit4

X

3

PLL N Divider Control bit3

PLL N Divider Control bit3

X

2

PLL N Divider Control bit2

PLL N Divider Control bit2

X

1

PLL N Divider Control bit1

PLL N Divider Control bit1

X

0

PLL N Divider Control bit0

PLL N Divider Control bit0

X

Note:

The default N value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value.

Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.

Byte11 PLL M Divide Ratio Control Register

Bit

Description

Contents

Default

7

N & M divider enable bit

0: N & M value will be determined by S [2:0] or

Byte8 bit[5:1].

1: N & M value will be determined by

Byte9,10,11.

0

6

PLL M Divider Control bit6

PLL M Divider Control bit6

X

5

PLL M Divider Control bit5

PLL M Divider Control bit5

X

4

PLL M Divider Control bit4

PLL M Divider Control bit4

X

3

PLL M Divider Control bit3

PLL M Divider Control bit3

X

2

PLL M Divider Control bit2

PLL M Divider Control bit2

X

1

PLL M Divider Control bit1

PLL M Divider Control bit1

X

0

PLL M Divider Control bit0

PLL M Divider Control bit0

X

Note:

The default M value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value.

Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.