M66288FP

REJ03F0156-0310 Rev.3.10 Apr.04.2008

Page 21 of 23

N-bit Delay 2

(Sliding timings of WRES and RRES at a cycle corresponding to delay length)

Reset cycle

0 cycle

1 cycle

2 cycle

n-1 cycle

Reset cycle

n cycle

0 cycle

n+1 cycle

1 cycle

n+2 cycle

2 cycle

n+3 cycle

3 cycle

Delay length n

WCK

RCK

WRES

Dn

(0)

(1)

(2)

(n-1)

(n+1)

(n+2)

(n+3)

(n)

(1)

(3)

RRES

(0)

Qn

(n-2)

(2)

·····Write side

·····Read side

262144

≥ n ≥ 16

WE, RE = "L"

N-bit Delay 3

(Sliding address by disabling RE at a cycle corresponding to delay length)

Reset cycle

0 cycle

1 cycle

2 cycle

n-1 cycle

n cycle

0 cycle

n+1 cycle

1 cycle

n+2 cycle

2 cycle

n+3 cycle

3 cycle

Delay length n

WCK

RCK

WRES

Dn

(0)

(1)

(2)

(n-1)

(n+1)

(n+2)

(n+3)

(n)

(1)

(3)

RRES

(0)

Qn

(n-2)

(2)

·····Write side

·····Read side

262144

≥ n ≥ 16

WE = "L"

RE

HIGH-Z