M66288FP

REJ03F0156-0310 Rev.3.10 Apr.04.2008

Page 2 of 23

Mode Descriptions Drawing

1K-word = 1024-word

Note1: Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line FIFO.

Maximum number of words on this mode is 256K-word. Line delay is achieved without outer connection.

Note2: Please refer to pin assignment tables in “Operation Description” of Mode 4, Mode 5, and Mode 8 for assignment of external pins,

Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.

256K-word

8-bit bus I/F

12-bit bus I/F

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

8

DA<7:0>

WCKA

WRESA

WEA

8

256K-w

x

8-bit

FIFO

QA<7:0>

RCKA

RRESA

REA

8

DB<7:0>

WCKB

WRESB

WEB

8

QB<7:0>

RCKB

RRESB

REB

256K-w

x

8-bit

FIFO

8

DC<7:0>

WCKC

WRESC

WEC

8

QC<7:0>

RCKC

RRESC

REC

256K-w

x

8-bit

FIFO

8

8

8

8

8

8

256K-w

x

8-bit

FIFO

256K-w

x

8-bit

FIFO

256K-w

x

8-bit

FIFO

DA<7:0>

WCKA

WRESA

WEA

QB<7:0>

QC<7:0>

QA<7:0>

RCKA

RRESA

REA

8

8

8

8

256K-w

x

8-bit

FIFO

256K-w

x

8-bit

FIFO

8

8

256K-w

x

8-bit

FIFO

DA<7:0>

WCKA

WRESA

WEA

QA<7:0>

RCKA

RRESA

REA

QB<7:0>

QC<7:0>

RCKC

RRESC

REC

DC<7:0>

WCKC

WRESC

WEC

12

256K-w

x

12-bit

FIFO

12

DA<11:0>

WCKA

WRESA

WEA

QA<11:0>

RCKA

RRESA

REA

DB<11:0>

WCKB

WRESB

WEB

QB<11:0>

RCKB

RRESB

REB

12

256K-w

x

12-bit

FIFO

12

12

256K-w

x

12-bit

FIFO

256K-w

x

12-bit

FIFO

12

12

12

DA<11:0>

WCKA

WRESA

WEA

QA<11:0>

RCKA

RRESA

REA

QB<11:0>

The three pieces of 256K-word x

8-bit FIFO can be operated

completely independently.

The three pieces of 256K-word x

8-bit FIFO are cascade-connected.

(Note 1)

The two pieces of 256K-word x

8-bit FIFO are cascade-connected

and, a piece of 256K-word x 8-bit

FIFO can be operated completely

independently. (Note 1)

The two pieces of 256K-word x

12-bit FIFO can be operated

completely independently.

(Note 2)

The two pieces of 256K-word x

12-bit FIFO are cascade-connected

(Note 1, Note 2)

3-system individual input

1-system input

(1) 1-system input

(2) 1-system input

2-system individual input.

1-system input

3-system individual output

The simultaneous output of the

1, 2, 3 line delay data.

(1) The simultaneous output of the

1, 2 line delay data.

(2) 1-system output

2-system individual output.

The simultaneous output of the

1, 2 line delay data.

768K-word

512K-word & 256K-word

512K-word

8-bit bus I/F

12-bit bus I/F

MODE 6

MODE 7

MODE 8

8

768K-w

x

8-bit

FIFO

8

DA<7:0>

WCKA

WRESA

WEA

QA<7:0>

RCKA

RRESA

REA

8

512K-w

x

8-bit

FIFO

8

DA<7:0>

WCKA

WRESA

WEA

QA<7:0>

RCKA

RRESA

REA

8

256K-w

x

8-bit

FIFO

8

DC<7:0>

WCKC

WRESC

WEC

QC<7:0>

RCKC

RRESC

REC

12

512K-w

x

12-bit

FIFO

12

DA<11:0>

WCKA

WRESA

WEA

QA<11:0>

RCKA

RRESA

REA

A piece of 768K-word x 8-bit

FIFO can be operated completely

independently.

A piece of 512K-word x 8-bit FIFO

and a piece of 256K-word x 8-bit

FIFO can be operated completely

independently.

A piece of 512K-word x 12-bit

FIFO can be operated completely

independently. (Note 2)

1-system input

2-system individual input

1-system input

1-system output

2-system individual output

1-system output