32C80 datasheet(53/60 Pages) RENESAS

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Page 53

5. Electrical Characteristics

BCLK

CSi

ADi

-3ns.min

BHE

ADi

/DBi

30ns.min

td(BCLK-RD)

tsu(DB-BCLK)

tdz(RD-AD)

8ns.max

ALE

td(BCLK-ALE)

18ns.max

td(AD-ALE)

th(ALE-AD)

th(BCLK-RD)

th(RD-AD)

td(BCLK-AD)

th(BCLK-CS)

th(RD-CS)

th(BCLK-ALE)

tcyc

Memory Expansion Mode and Microprocessor Mode

(when accessing external memory space and using the multiplexed bus)

0ns.min

BCLK

CSi

ADi

BHE

ADi

/DBi

WR,WRL,

WRH

ALE

th(BCLK-WR)

18ns.max

tac2(AD-DB)

[ Read Timing ] (2

φ +2φ Bus Cycles)

Address

(1)

td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is a

φ + bφ, n=a)

th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is a

φ + bφ, n=a)

th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min

tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a

φ + bφ, m=(b x 2)-1)

tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is a

φ + bφ, p={(a+b-1) x 2}+1)

NOTE:

1. Varies with operation frequency:

(1)

[ Write Timing ] (2

φ +2φ Bus Cycles)

Address

td(AD-ALE)=(tcyc/2 x n - 20)ns.min

(if external bus cycle is a

φ + bφ, n=a)

th(ALE-AD)=(tcyc/2 x n -10)ns.min

(if external bus cycle is a

φ + bφ, n=a)

th(WR-AD)=(tcyc/2-10)ns.min,

th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-20)ns.min

td(DB-WR)=(tcyc/2 x m-25)ns.min

(if external bus cycle is a

φ + bφ, m=(b x 2)-1)

NOTE:

2. Varies with operation frequency:

Measurement Conditions:

• VCC1=VCC2=3.0 to 3.6V

• Input high and low voltage:

VIH=1.5V, VIL=0.5V

• Output high and low voltage:

VOH=1.5V, VOL=1.5V

Vcc1=Vcc2=3.3V

18ns.max

td(BCLK-WR)

th(WR-AD)

(2)

th(BCLK-AD)

0ns.min

Data output

th(ALE-AD)

-2ns.min

td(BCLK-ALE)

th(BCLK-ALE)

18ns.max

0ns.min

th(WR-CS)

td(AD-ALE)

td(BCLK-CS)

td(BCLK-AD)

th(BCLK-CS)

td(DB-WR)

th(WR-DB)

tcyc

(2)

18ns.max

0ns.min

tac2(RD-DB)

-2ns.min

td(BCLK-CS)

th(RD-DB)

th(BCLK-AD)

0ns.min

Data input

Address

tcyc=

f(BCLK)

Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (2)

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