32C80 datasheet(41/60 Pages) RENESAS

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Page 41

5. Electrical Characteristics

Figure 5.2 VCC1=VCC2=5V Timing Diagram (1)

BCLK

18ns.max

-5ns.min

Hi-Z

0ns.min

tsu(DB-BCLK)

td(BCLK-RD)

26ns.min(1)

CSi

td(BCLK-CS)

18ns.max(1)

ADi

th(BCLK-AD)

-3ns.min

th(BCLK-CS)

-3ns.min

BHE

tcyc

td(BCLK-AD)

0ns.min

tac1(AD-DB)(2)

WR,WRL,

WRH

18ns.max

-5ns.min

BCLK

CSi

td(BCLK-CS)

18ns.max

ADi

td(BCLK-AD)

18ns.max

-3ns.min

tcyc

BHE

DBi

td(BCLK-WR)

th(WR-DB)(3)

td(DB-WR)=(tcyc x m-20)ns.min

(if external bus cycle is a

φ+bφ, m=b)

th(WR-DB)=(tcyc/2-10)ns.min

th(WR-AD)=(tcyc/2-10)ns.min

th(WR-CS)=(tcyc/2-10)ns.min

tw(WR)=(tcyc/2 x n-15)ns.min

(if external bus cycle is a

φ+bφ , n=(bx2)-1)

Vcc1=Vcc2=5V

th(BCLK-RD)

th(RD-DB)

th(RD-AD)

th(RD-CS)

th(BCLK-WR)

th(BCLK-AD)

th(BCLK-CS)

th(WR-CS)(3)

th(WR-AD)(3)

tw(WR)(3)

tac1(RD-DB)(2)

18ns.max(1)

[ Read Timing ] (1

φ +1φ Bus Cycle)

[ Write timing ] (1

φ +1φ Bus Cycle)

NOTE:

3. Varies with operation frequency:

Measurement Conditions:

• VCC1=VCC2=4.2 to 5.5V

• Input high and low voltage: VIH=2.5V, VIL=0.8V

• Output high and low voltage: VOH=2.0V, VOL=0.8V

Memory Expansion Mode and Microprocessor Mode

(when accessing an external memory space)

NOTES:

1. Values guaranteed only when the microcomputer is used independently.

A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).

2. Varies with operation frequency:

tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a

φ + bφ, m=(b x 2)+1)

tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is a

φ + bφ, n=a+b)

td(DB-WR)(3)

tcyc=

f(BCLK)

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