CYRF7936
Document #: 001-48013 Rev. **
Page 2 of 21
Functional Description
The CYRF7936 CyFi™ Transceiver is a Radio IC designed for low-power embedded wireless applications. Combined with
Cypress’s PSoC programmable system-on-chip and a CyFi network protocol stack, CYRF7936 can be used to implement a
complete CyFi wireless system.
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
RFBIAS
NC
NC
VBAT2
VCC
VBAT1
XTAL
VCC
NC
NC
NC
SS
SCK
IRQ / GPIO
MOSI/ SDAT
MISO/ GPIO
XOUT/ GPIO
PACTL/ GPIO
NC
NC
* E- PAD Bottom Side
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
CYRF7936
CyFi Transciever
40 lead QFN
Corner
tabs
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
Name
Type
Default
Description
13
RFN
IO
I
Differential RF signal to and from antenna.
11
RFP
IO
I
Differential RF signal to and from antenna.
10
RFBIAS
O
O
RF IO 1.8V reference voltage.
30
PACTL
IO
O
Control signal for external PA, T/R switch, or GPIO.
1
XTAL
I
I
12 MHz crystal.
29
XOUT
IO
O
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
25
SCK
I
I
SPI clock.
28
MISO
IO
Z
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS# is deasserted.
27
MOSI
IO
I
SPI data input pin (Master Out Slave In), or SDAT.
24
SS#
I
I
SPI enable, active LOW assertion. Enables and frames transfers.
26
IRQ
IO
O
Interrupt output (configurable active HIGH or LOW), or GPIO.
34
RST
I
I
Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically
connect through a 0.47
μF capacitor to VBAT. Must have RST = 1 event the
first time power is applied to the radio. Otherwise the state of the radio control
registers is unknown.
37
LVD
O
PMU inductor/diode connection, when used. If not used, connect to GND.
40
VREG
Pwr
PMU boosted output voltage feedback.
35
VDD
Pwr
Decoupling pin for 1.8V logic regulator, connect through a 0.47
μF capacitor
to GND.
6, 8, 38
VBAT(0-2)
Pwr
VBAT = 1.8V to 3.6V. Main supply.
3, 7, 16
VCC
Pwr
VCC = 2.4V to 3.6V. Typically connected to VREG.
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