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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MSC7116 датащи(PDF) 37 Page - Freescale Semiconductor, Inc |
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MSC7116 датащи(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 60 page  MSC7116 Data Sheet, Rev. 13 Freescale Semiconductor 37 2.5.9 UART Timing 2.5.10 EE Timing Figure 24 shows the signal behavior of the EE pin. Table 27. UART Timing No. Characteristics Expression Min Max Unit — Internal bus clock (APBCLK) FCORE/2 — 133 MHz — Internal bus clock period (1/APBCLK) TAPBCLK 7.52 — ns 400 URXD and UTXD inputs high/low duration 16 × TAPBCLK 120.3 — ns 401 URXD and UTXD inputs rise/fall time — 5 ns 402 UTXD output rise/fall time — 5 ns Figure 21. UART Input Timing Figure 22. UART Output Timing Table 28. EE0 Timing Number Characteristics Type Min 65 EE0 input to the core Asynchronous 4 core clock periods 66 EE0 output from the core Synchronous to core clock 1 core clock period Notes: 1. The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. 2. Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. 3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 23. EE Pin Timing UTXD, URXD 400 inputs 400 401 401 UTXD Output 402 402 EE0 In 65 EE0 Out 66 |
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